Publications

Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
Yuyang Zou, Youwei Xiao, Yansong Xu, Chenyun Yin, Yuhao Luo, Yitian Sun, Ruifan Xu, Renze Chen, Yun Liang
arXiv High-Level Synthesis Hardware Description Languages Retargetable Compiler
DOI

SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
Youwei Xiao, Yuyang Zou, Yun Liang
arXiv High-Level Synthesis
DOI

Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Youwei Xiao, Zizhang Luo, Weijie Peng, Yuyang Zou, Yun Liang
arXiv Hardware Description Languages
DOI

APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang
ICCAD 2025 Invited Paper High-Level Synthesis Hardware Description Languages Processor Specialization Retargetable Compiler
DOI

Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis
Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang
MICRO 2024 High-Level Synthesis
DOI Code

POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
Xiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong Jiang, Yun Liang
FPGA 2024 High-Level Synthesis
DOI Code

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang
FPGA 2024 Hardware Description Languages
DOI Code

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation
Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang
MICRO 2023
DOI Code

Hector: Multi-Level Intermediate Representation for Hardware Synthesis
Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang
ICCAD 2022 High-Level Synthesis
DOI Code

Publications

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