High-Level Synthesis
High-Level Synthesis
Advanced high-level synthesis techniques for efficient translation from behavioral descriptions to optimized hardware.
We develop advanced high-level synthesis techniques that enable efficient translation from high-level behavioral descriptions to optimized hardware implementations. Our work focuses on:
ISAX-Specific Scheduling
SDC-based scheduling with ISAX-specific constraints, optimizing the timing and resource utilization of custom instructions.
Hybrid Latency-Sensitive/-Insensitive Design
Combining static and dynamic HLS scheduling techniques to generate pipelined datapaths for efficient ISAX acceleration.
High-performance Architecture Support
Diving into HLS analysis and transform techniques as well as spatial-temporal transformation to create design of high parallelism to meet performance requirements.
Related Publications
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Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
Yuyang Zou, Youwei Xiao, Yansong Xu, Chenyun Yin, Yuhao Luo, Yitian Sun, Ruifan Xu, Renze Chen, Yun Liang
arXiv
DOI -
SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
Youwei Xiao, Yuyang Zou, Yun Liang
arXiv
DOI -
APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang
ICCAD 2025 Invited Paper
DOI -
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis
Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang
MICRO 2024
DOI Code -
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
Xiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong Jiang, Yun Liang
FPGA 2024
DOI Code -
Hector: Multi-Level Intermediate Representation for Hardware Synthesis
Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang
ICCAD 2022
DOI Code