Hardware Description Languages
Hardware Description Languages
Pioneering new description abstractions to hardware/ISAX design.
We dive into abstraction and compilation research for hardware description and generation.
Cement Series
What is the right abstraction to describe hardware? RTL is general and brings troubles according to its low-level, structural nature. We prefer software-style description! Cement at FPGA 2024 explored bringing software procedural description to RTL world. The subsequent version, CMT2, further explored the transactional (or rule-based, Bluespec-style) hardware description. We create DSLs in Rust and also migrate the features to MLIR ecosystem to support the APS project.
CADL (Cross-level Architecture Description Language)
Unified language for ISAX specification from high-level behavior to low-level implementation. CADL bridges the gap between algorithmic description and hardware realization. We want it to be the single specification for ISAX functionality description, hardware specification, and compiler targets.
Related Publications
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Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
Yuyang Zou, Youwei Xiao, Yansong Xu, Chenyun Yin, Yuhao Luo, Yitian Sun, Ruifan Xu, Renze Chen, Yun Liang
arXiv
DOI -
Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Youwei Xiao, Zizhang Luo, Weijie Peng, Yuyang Zou, Yun Liang
arXiv
DOI -
APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang
ICCAD 2025 Invited Paper
DOI -
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang
FPGA 2024
DOI Code