Abstract

The rapid evolution of domain-specific applications demands specialized processors with competitive performance and efficiency. While the open RISC-V instruction set architecture (ISA) simplifies the adoption of custom instruction extensions (ISAXs), the overall process of processor specialization remains challenging. It involves a complex interplay of multiple tasks, including behavioral architecture description, hardware synthesis and implementation, processor-ISAX adaptation, and compiler co-generation. Existing RISC-V ecosystems often address these challenges manually, lacking a fully automated and integrated solution. This tutorial introduces APS for agile processor specialization based on Multi-Level Intermediate Representation (MLIR). MLIR can support multiple different requirements in a unified infrastructure. APS provides a unified framework of powerful, open-source EDA and compiler tools for seamless hardware-software co-design, empowering designers to navigate the complexities of specialization with greater ease and efficiency.

What You Will Learn

This tutorial will highlight the methodology and open-source tools within the APS framework, demonstrating a complete software-hardware co-design flow:

• High-level ISAX Description: Describe ISAXs’ behavior at a high, near-software level
• MLIR-based HLS: Synthesize efficient hardware architecture through an MLIR-based high-level synthesis flow with powerful debugging features
• Transactional Hardware Generation: Translate synthesis results to low-level implementation via MLIR transformations
• Processor-ISAX Adaptation: Model the interaction between base processor and ISAX units through a unified ADL interface
• Compiler Infrastructure: Automated and efficient utilization of custom ISAXs with compiler feedback

Setup Instructions

We’ve released the APS framework as an open-source project on GitHub: pku-liang/aps-mlir, which includes the tools, examples, and documentation needed for the hands-on session.

We provide two options for hands-on setup:

1. We’ll provide SSH access to a pre-configured APS environment during the tutorial.
2. You can set up the APS framework on your local machine before the tutorial using the instructions below.

Prerequisites

• Linux (Ubuntu 22.04 recommended)
• Pixi package manager

Installation

1. Clone the repository:

   git clone https://github.com/pku-liang/aps-mlir.git
   cd aps-mlir
   

2. Setup chipyard

   pixi run fix-verilator
   pixi run setup-ortools
   pixi run setup-yosys-slang
   pixi run setup-firtool
   pixi run setup-chipyard
   

3. Build CIRCT and APS passes:

   rm -rf circt/build
   pixi run setup
   pixi run build
   

Quick Start

The tutorial/ directory contains example CADL files and scripts. Here’s a simple example (tutorial/cadl/hello.cadl):

#[opcode(7'b0101011)]
#[funct7(7'b0000000)]
rtype hello(rs1: u5, rs2: u5, rd: u5) {
  let a: u32 = _irf[rs1];
  let b: u32 = _irf[rs2];
  let c: u32 = a + b;
  _irf[rd] = c;
}

See the tutorial/ directory for more examples including matrix operations (vgemv3d.cadl) and distance calculations (v3ddist_vv.cadl).

Full ASIP Pipeline

# Enter pixi environment
pixi shell
# Synthesize CADL to hardware
./tutorial/a1-ex1synth.sh
# Compile test program with custom instruction
./tutorial/a2-ex1compile.sh
# Full SoC simulation and synthesis
./tutorial/a6-ex1sim.sh
./tutorial/a7-ex1yosys.sh

Target Audience

This tutorial is formulated to be broadly interesting and useful to:

• Students and researchers in computer architecture and EDA
• Faculty members interested in domain-specific hardware
• Practicing engineers in EDA and domain-specific hardware development communities

Speakers

Yun (Eric) Liang

Professor, Peking University

Professor Yun Liang leads the APS project at Peking University.

Youwei Xiao

PhD Student, Peking University

Youwei Xiao is a 4th-year PhD student working on the APS framework. He takes wide interests in software techniques for hardware synthesis, computer architecture, and compilers.

Yuyang Zou

MS Student, Peking University

Yuyang Zou is a master student working on the APS framework, focusing on hardware high-level synthesis and FPGA prototyping.

Chenyun Yin

Undergrad Student, Peking University

Chenyun Yin is an undergraduate researcher involved in the APS framework, specializing in compiler technology and hardware architecture.

Yitian Sun

Undergrad Student, Peking University

Yitian Sun is an undergraduate student working on the APS framework, focusing on software techniques for hardware synthesis.